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| INDEX MX23C8100 8M-BIT MASK ROM (8/16 BIT OUTPUT) FEATURES * Bit organization - 1M x 8 (byte mode) - 512K x 16 (word mode) * Fast access time - Random access: 100ns (max.) * Current - Operating: 60mA - Standby: 50uA * Supply voltage - 5V10% * Package - 44 pin SOP (500mil) - 42 pin PDIP (600mil) - 48 pin TSOP (20mm x 12mm) ORDER INFORMATION Part No. MX23C8100PC-10 MX23C8100PC-12 MX23C8100PC-15 MX23C8100MC-10 MX23C8100MC-12 MX23C8100MC-15 MX23C8100TC-10 MX23C8100TC-12 MX23C8100TC-15 Access Time 100ns 120ns 150ns 100ns 120ns 150ns 100ns 120ns 150ns Package 42 pin PDIP 42 pin PDIP 42 pin PDIP 44 pin SOP 44 pin SOP 44 pin SOP 48 pin TSOP 48 pin TSOP 48 pin TSOP Note: 40-TSOP and 48-RTSOP support word mode only, not for byte mode. PIN CONFIGURATION 42 PDIP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE/CE VSS OE/OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC PIN DESCRIPTION Symbol A0~A18 D0~D14 D15/A-1 CE/CE OE/OE Byte VCC VSS NC Pin Function Address Inputs Data Outputs D15 (Word Mode)/ LSB Address (Byte Mode) Chip Enable Input Output Enable Input Word/ Byte Mode Selection Power Supply Pin Ground Pin No Connection 44 SOP NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE/CE VSS OE/OE D0 D8 D1 D9 D2 D10 D3 D11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A1 D7 D14 D6 D13 D5 D12 D4 VCC MX23C8100 48 TSOP (for word mode only) NC A16 A15 A14 A13 A12 A11 A10 A9 A8 NC VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE/CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC NC D11 D3 D10 D2 D9 D1 D8 D0 OE/OE VSS VSS MX23C8100 MX23C8100 P/N:PM0138 REV. 4.2, SEP. 01, 1997 1 INDEX MX23C8100 MODE SELECTION CE/CE L/H H/L H/L H/L OE/OE X L/H H/L H/L Byte X X H L D15/A-1 X X Output Input D0~D7 High Z High Z D0~D7 D0~D7 D8~D15 High Z High Z D8~D15 High Z Mode Word Byte Power Stand-by Active Active Active BLOCK DIAGRAM A0/(A-1) A18 CE BYTE OE Address Buffer Memory Array Sense Amplifier Word/ Byte Output Buffer D0 D15/(D7) ABSOLUTE MAXIMUM RATINGS Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VCC Topr Tstg Ratings -0.5V to 7.0V 0 to 70 C C -65 to 125 C C Note: minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC voltage on input or I/ O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. P/N:PM0138 REV. 4.2, SEP. 01, 1997 2 INDEX MX23C8100 DC CHARACTERISTICS (Ta = 0C ~ 70C, VCC = 5V10%) Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance Symbol VOH VOL VIH VIL ILI ILO ICC1 ISTB1 ISTB2 CIN COUT MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 10uA 10uA 60mA 1mA 50uA 10pF 10pF Conditions IOH = -1.0mA IOL = 2.1mA 0V, VCC 0V, VCC tRC=100ns, all output open CE=VIH CE> VCC - 0.2V Ta = 25 f = 1MHZ C, Ta = 25 f = 1MHZ C, AC CHARACTERISTICS (Ta = 0C ~ 70C, VCC = 5V10%) Item Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time Output Hold After Address Output High Z Delay Symbol tRC tAA tACE tOE tOH tHZ 23C8100-10 MIN. MAX. 100ns 100ns 100ns 50ns 10ns 20ns 23C8100-12 MIN. MAX. 120ns 120ns 120ns 60ns 10ns 20ns 23C8100-15 MIN. MAX. 150ns 150ns 150ns 70ns 10ns 20ns Note:Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range not tested. P/N:PM0138 REV. 4.2, SEP. 01, 1997 3 INDEX MX23C8100 AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~2.4V 10ns 1.5V 0.8V and 2.0V See Figure IOH (load)=-1mA DOUT IOL (load)=2.1mA C<100pF Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. TIMING DIAGRAM RANDOM READ ADD ADD tACE ADD tRC ADD CE OE tOE tOH VALID tHZ VALID tAA DATA VALID P/N:PM0138 REV. 4.2, SEP. 01, 1997 4 INDEX MX23C8100 REVISION HISTORY Revision 4.2 Description DC Characteristics: The standby current (CMOS) ISTB2 is changed as 50us instead of 100uA. AC Characteristics: Deleted 200ns grade item. The output enable time (tOE) is changed as 60ns instead of 70ns in 120ns grade item, and 70ns instead of 80ns in 150ns grade item. The output high Z delay is changed as 20ns instead of 70ns. Page Date SEP/01/1997 P/N:PM0138 REV. 4.2, SEP. 01, 1997 5 INDEX MX23C8100 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 6 |
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